If you didn’t read the post I added a couple years before this one, be sure to read it first. It describes my initial discovery of the TypeStore systems.
http://www.vintagevolts.com/typestore/
Three EPROMs and a Trail of TTL: Unearthing the TypeStore’s Secret Map
The TypeStore’s physical design makes one thing crystal clear—it was built to do something quite specific. Tucked within its metal shell are three 2764 EPROMs, perched on sockets as if waiting for their moment in the spotlight. Naturally, the hunt began by asking: where do these EPROMs live in memory? Answering that question seemed simple enough. But just beneath the surface, the answer unlocked a chain of logic that led to something far more complex and deliberate.
Each 2764 stores 8KB of data, and common sense might suggest they’re mapped linearly—0000–1FFFh, 2000–3FFFh, and 4000–5FFFh, for instance. But following the traces and decoding logic blocks said otherwise. These chips weren’t just laid down for convenience—they were carefully curated into a broader narrative told in TTL logic.
Memory Mapping, the Hard Way
The decoding process started with the 74LS139, a dual 2-to-4 decoder. Each half of this chip decodes two address lines into four select lines. One section was found to respond to address lines A13 and A14, effectively splitting the 8KB windowed spaces into four distinct regions. One output triggered ROM-related circuitry, another RAM, and the others something yet unexplored.
But that wasn’t the whole story. These decoder outputs didn’t activate the EPROMs directly—they instead flowed through a series of logic gates, mostly OR and NOR combinations from 74LS32 and 74LS27 ICs. The result: device selection was gated by more than just address bits. It included timing cues, and possibly even CPU synchronization events.
Then came the buffers. Signals from the decoder fed into a 74LS241, which wasn’t just buffering the ROM enable line—it was treating it as one of several dynamic signals, each of which could be gated onto the bus only under specific conditions. In parallel, a 74LS374 octal flip-flop latched critical control bits and held them steady when the bus needed to shift roles—possibly between memory access and peripheral I/O or between one processor and another.
The EPROMs themselves—located at strategic board locations and wired into shared control lines—appear to be selected based on a blend of static address decoding and dynamic enable logic. Their /CE (Chip Enable) and /OE (Output Enable) pins receive signals routed through several layers of logic. This arrangement likely divides control between multiple bus masters or separates system firmware from device configuration data.
One Line, Two Masters
A pivotal discovery emerged during signal tracing: 1Y1 of the 74LS241 (U25) was directly connected to Q1 of the 74LS374 (U26)—both outputs. This is not a configuration seen in typical textbook circuits. But here, it was entirely intentional.
Thanks to the tri-state nature of these devices, their outputs can coexist on the same line so long as only one drives the bus at a time. When the buffer (U25) is enabled, it forwards real-time data from an earlier stage. When the latch (U26) takes over, it holds that data in place, allowing other parts of the system to act on a stable value.
This connection likely represents a shared bus line, with each chip assigned a role during different timing windows. That one line could represent a control bit, an address latch output, or even a handshake between CPUs or between CPU and I/O devices.
Timing is Everything
Signals like clock inputs and output enables formed a second layer of intrigue. U26’s clock pin was connected to a shared timing source that also reached U31 (a 74LS74 flip-flop) and the enable line for U25’s outputs. This setup strongly suggests that data moves between these components in a synchronized, state-driven process—not just passively based on address lines.
By analyzing when each chip is allowed to speak and when it must be silent, a portrait of bus arbitration emerges. The TypeStore doesn’t just route signals—it negotiates them, staging which device gets to place its bits on the bus, and when. This level of coordination hints at a broader goal: allowing the system to act as both a word processor and a peripheral brain for the Wheelwriter, shuttling characters, cursor commands, and control codes without crashing into its own memory map.
One Question, Many Answers
All of this stemmed from that single question: where are the three EPROMs mapped in memory? What began as a straightforward bit of exploration snowballed into a deep reconstruction of how address decoding, bus timing, and logic staging were orchestrated to form a reliable system.
It turns out the EPROMs may not merely be slotted into addresses—they seem to be activated through layers of logic interlock, implying that their contents may be dynamically enabled based on mode, CPU control, or external requests. This suggests some fascinating possibilities still to explore: the secondary 8085 CPU that exists in the system perhaps, or dynamic bank switching, or feature-based firmware selection.
And with that, the TypeStore continues to reveal that it’s more than just a forgotten peripheral—it’s an elegantly designed collaboration between logic and timing, purpose-built to bridge the analog and digital worlds of its time. Well… this is my project, so I can certainly think about it that way. 😎
Decoding, Documented
As reverse engineering progressed from simple pin tracing to signal timing and bus behavior, the TypeStore transformed from a mysterious box of parts into a logic-driven machine with real architectural intent. The mapping of its three EPROMs wasn’t just about memory addresses—it was about understanding how every signal handshake, every gated buffer, and every latched line fit together to make this word processing bridge work.
And that’s the heart of the story so far: the TypeStore wasn’t just a peripheral; it was a carefully orchestrated digital interpreter. One that buffered, latched, and decoded in perfect rhythm with the IBM Wheelwriter’s operations, offering screen-based typing at a time when floppy disks were still a luxury.
Each new trace brings the system into sharper focus. With signals mapped, schematics reconstructed, and EPROMs starting to speak again through disassembled code, the TypeStore project is shifting gears. No longer a black box, it’s now a puzzle being steadily solved—signal by signal, line by line, byte by byte.
The story’s next chapters in this blog series may continue unravelling the memory map of this dual-CPU system, follow the software’s inner workings, explore how the two 8085 processors might be coordinating efforts, or ultimately piece together a working simulation or hardware interface to bring the TypeStore back to life—or at least make it speak again in silicon.
There’s still a keyboard’s worth of work ahead, but researching one EPROM mystery has opened the door to understanding the entire machine.
